CWE-1315: Improper Setting of Bus Controlling Capability in Fabric End-point

MITRE CWE weakness

Description

The bus controller enables bits in the fabric end-point to allow responder devices to control transactions on the fabric.

To support reusability, certain fabric interfaces and end points provide a configurable register bit that allows IP blocks connected to the controller to access other peripherals connected to the fabric. This allows the end point to be used with devices that function as a controller or responder. If this bit is set by default in hardware, or if firmware incorrectly sets it later, a device intended to be a responder on a fabric is now capable of controlling transactions to other devices and might compromise system security.

Common consequences

• Access Control: Modify Memory, Read Memory, Bypass Protection Mechanism

Mitigations

Architecture and Design — For responder devices, the register bit in the fabric end-point that enables the bus controlling capability must be set to 0 by default. This bit should not be set during secure-boot flows. Also, writes to this register must be access-protected to prevent malicious modifications to obtain bus-controlling capability.

Implementation — For responder devices, the register bit in the fabric end-point that enables the bus controlling capability must be set to 0 by default. This bit should not be set during secure-boot flows. Also, writes to this register must be access-protected to prevent malicious modifications to obtain bus-controlling capability.

System Configuration — For responder devices, the register bit in the fabric end-point that enables the bus controlling capability must be set to 0 by default. This bit should not be set during secure-boot flows. Also, writes to this register must be access-protected to prevent malicious modifications to obtain bus-controlling capability.

References

• CWE page: https://cwe.mitre.org/data/definitions/1315.html
• CWE list: https://cwe.mitre.org/data/index.html